3D-Stacked Many-Core Architecture for Biological Sequence Analysis Problems

Test-Architecture Optimization for 3D Stacked ICs

TSV-based 3D-SICs significantly impact core-based systemon-chip (SOC) design. Testing of core-based dies in 3D-SICs introduces new challenges [1], [2]. In order to test the dies in a stack, the embedded cores, and the TSVs, a test access mechanism (TAM) must be included on the die to transport test data to the cores, and a 3D TAM is needed to transfer test data to the die from the stack input/o...

Nanophotonic Interconnects and 3D-stacked Technology for Future Many-core Architectures

Xiang Zhang and Ahmed Louri Electrical and Computer Engineering, University of Arizona, Tucson, AZ 85721 E-mail:{ zxkidd, louri}@ece.arizona.edu Abstract: We explore silicon photonics and 3D stacked technology to implement a photonic network-on-chips. The proposed scheme provides 2.56 Tb/sec bandwidth with a much reduced power consumption and latency compared to any leading on-chip photonic net...

Many-core architecture for programmable hardware accelerator

Photonic Many-Core Architecture Study

Several recent device technology developments have been fundamentally changing the microprocessor architecture design space. These developments include photonic interconnects, feature size reduction, 3D fabrication, and aggressive energy management. These technologies create a large parameter space of possible future architectures. The focus of this talk and research effort is to demonstrate a ...

Power-Aware Core Management Scheme for Heterogeneous Many-Core Architecture

OF THE THESIS Power-Aware Core Management Scheme for Heterogeneous Many-Core Architecture By Myoung-Seo Kim Master of Science in Computer Engineering University of California, Irvine, 2015 Professor Jean-Luc Gaudiot, Chair The main challenge in designing the future heterogeneous many-core architecture on the same chip is to provide a solution that has low power consumption, in addition to trade...